2013-01-24 14:22:53 -

SUNNYVALE, CA--(Marketwire - January 24, 2013) -   Real Intent : www.realintent.com/ , Inc., a leading provider of EDA advanced sign-off verification solutions, today announced the next release of its Meridian Constraints : www.realintent.com/real-intent-products/meridian-constraints/ product for comprehensive design constraint management. This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent's product leadership in delivering what the company believes are the industry's fastest-performance and highest-capacity RT-level verification tools. 
New features include:

• Constraints equivalency checks for top-level versus block-level of design to ensure that block-level constraints have been aggregated correctly in the complete design, or that constraints are correctly propagated downward for individual block verification


• An enhanced timing exceptions verification engine with greater speed and coverage


• Significant enhancements to the SystemVerilog support and associated error handling


• Verdi3 integration -- the industry-leading debug platform from Synopsys (formerly SpringSoft)

Sarath Kirihennedige, senior manager of product engineering at Real Intent, said, "Designers need to write SDC constraints based on timing goals for new IP and merge these with SDC constraints from existing or imported IP. Unfortunately, until now they had to rely on spreadsheets and manual methods to organize this data. Meridian Constraints provides the design automation software to meet the needs of design teams to create, manage, and verify all of the SDC. It ensures the SDC completely covers the design, correctly matches the functional and timing goals and is consistent between different blocks and levels in the design. Having correct and complete constraints and associated clock definitions ensures timing goals are met. It enables correct clock domain crossing analysis, resulting in ultimate confidence for users, and successful low-power and X-verification flows." To see a video interview about SDC constraints management by Sarath Kirihennedige, please visit  www.youtube.com/watch?v=aeff95l49D0 : www.youtube.com/watch?v=aeff95l49D0

Comprehensive SDC Management and Verification

Meridian Constraints offers high-performance constraint validation, constraints template generation, coverage analysis, equivalence checking and timing exception verification capabilities for timing constraints employed across all phases of the synthesis and implementation flow. Real Intent believes no other product delivers such comprehensive SDC management and verification capabilities.

Availability
The new release of Meridian Constraints is available now. Pricing depends on product configuration. For more information, please email info@realintent.com : mailto:info@realintent.com

About Real Intent
Companies worldwide rely on Real Intent's EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent's Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com : www.realintent.com/ for more information.

Acronyms

CDC: Clock Domain Crossing
EDA: Electronic Design Automation
HDL: Hardware Description Language
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
SoC: Systems-on-Chip

Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.




Image Available: www.marketwire.com/library/MwGo/2013/1/23/11G003425/Meridian-1ea .. : www.marketwire.com/library/MwGo/2013/1/23/11G003425/Meridian-1ea ..



Embedded Video Available: www.youtube.com/watch?v=aeff95l49D0 : www.youtube.com/watch?v=aeff95l49D0






Press contact:

Sarah Miller
for Real Intent
ThinkBold Corporate Communications
231-264-8636
sarah@thinkbold.com : docid: 20130124_11G003425-001.nitf -->