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EU-Funded SYNAPTIC Project Delivers State-of-the-Art Design-Synthesis Tool Flow

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Copyright © Thomson Reuters 2013. All rights reserved.
2013-03-18 15:04:55 -

Milan, Italy - March 18, 2013 -- A joint industry/academia consortium, supported
by the European Union's Seventh Framework Programme, has reported the successful
conclusion of a three-year project and the release of its design-synthesis tool
flow and related litho-friendly cell libraries and evaluation metrics.

The SYNAPTIC research project included eight partner organizations from across
Europe and Brazil who worked together to develop innovative regularity-centric
design methods and Electronics Design Automation (EDA) tools. The goal of the
project was to reduce limitations in both logical and physical implementation
effectiveness associated with technology scaling and advanced sub-wavelength

Through the development of new pattern-aware logic synthesis and implementation
techniques, SYNAPTIC addressed critical problems such as systematic variability
reduction, DFM (Design for Manufacturing) and yield improvement (at the cell,
IP/macro, and system levels), sophisticated area/performance 
trade-offs, and system-level/architectural predictability and sign-off, for the European semiconductor industry. The goal has been to sustain the scaling predicted by Moore's Law into advanced nanometer technologies. The libraries, tools, and methodologies developed within the SYNAPTIC project can enable synthesis and implementation of several designs based on a reduced set of regular layout patterns with similar area, power consumption, and timing performance. These efforts have demonstrated that the beneficial impact of regularity on variability and manufacturability does not have detrimental effects on the other metrics. The yield metric and models developed in SYNAPTIC show that a significant yield improvement can be achieved for large process windows, which immediately translate into cost benefits, increased productivity, and faster time-to-market by reducing the effort on OPC (Optical Proximity Correction) before fabrication. The process flow developed by SYNAPTIC is stable and delivers consistent results, and is ready for an evaluation on industrial designs. By successfully reaching all the milestones and enabling the exploitation of the regularity concept at different stages of design development and implementation, and in a new class of innovative synthesis and automatic library generation tools, the SYNAPTIC project has been instrumental in aligning the European semiconductor industry to global Integrated Device Manufacturers (IDMs) and Far East foundries, increasing the competitiveness of semiconductor and EDA companies in Europe. Moreover, by thoroughly disseminating its activities throughout the project, SYNAPTIC has also contributed to making the European academic research in this field more visible worldwide. For additional information on the SYNAPTIC project go to: www.synaptic- or contact Giuseppe Desoli at The SYNAPTIC Consortium partners include design optimization company Nangate; Europe's largest IDM, STMicroelectronics; Thales (France), which is the European global technology leader for the aerospace, space, defense, security and transportation markets; and imec (Belgium), which performs world-leading research in nanoelectronics. Three leading universities, Politecnico di Milano (Italy), Universitat Polit├Ęcnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) brought significant and highly specialised technology contributions to the joint research. The final partner, Leading Edge, participated as a consultancy company specializing in the introduction of innovative EDA technologies to the European marketplace. SYNAPTIC Project Conclusion: This announcement is distributed by Thomson Reuters on behalf of Thomson Reuters clients. The owner of this announcement warrants that: (i) the releases contained herein are protected by copyright and other applicable laws; and (ii) they are solely responsible for the content, accuracy and originality of the information contained therein. Source: STMicroelectronics via Thomson Reuters ONE [HUG#1685905]

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